1. Technical Field
The disclosed embodiments relate to a Delay-Locked Loop (DLL) that delays a clock signal by an amount of time that is substantially constant and independent of variations in the duty cycle of the clock signal.
2. Background Information
FIG. 1 (Prior Art) is a diagram of a Delay-Locked Loop (DLL) 1 that receives an incoming clock signal CKREF on input lead 2 and outputs three delayed versions of CKREF. A signal OUT3/3 on output lead 3 is a replica of signal CKREF that is delayed by a programmable delay time with respect to CKREF. Signal OUT2/3 on output lead 4 is a replica of signal CKREF that is delayed by two thirds of the programmable delay time. Signal OUT1/3 on output lead 5 is a replica of signal CKREF that is delayed by one third of the programmable delay time. The programmable delay time is determined by the ratio of a current IUP that charges up a capacitor 6 to a current IDN that discharges capacitor 6. The magnitude of up current IUP is determined by programmable current source 7. The magnitude of down current IDN is determined by programmable current source 8. The voltage signal on capacitor 6 is filtered and converted by a circuit 9 into a control current IFILT. Control current IFILT in this example is the supply current for a chain of inverters 10. The chain of inverters 10 delays the signal CKREF, thereby generating the output signals OUT1/3, OUT2/3 and OUT3/3. The larger the supply current IFILT, the smaller the delay. The smaller the supply current IFILT, the larger the delay. A feedback control loop involving a NOR gate 11 controls the delay through the chain of inverters 10 such that the charge supplied to capacitor 6 each cycle equals the charge withdrawn from capacitor 6 each cycle.
FIG. 2 (Prior Art) is a waveform diagram that illustrates operation of DLL 1. Waveforms 12 illustrate operation of DLL 1 when CKREF has a 50/50 duty cycle. Waveforms 13 illustrate operation of DLL 1 when CKREF has a 45/55 duty cycle. Waveforms 14 illustrate operation of DLL 1 when CKREF has a 55/45 duty cycle. The voltage on capacitor 6 increases during the time NOR gate 11 outputs a digital logic low, and the voltage on capacitor 6 decreases during the time NOR gate 11 outputs a digital logic high. The control loop adjusts the delay of the chain of inverters 10 such that the charge up charge (charging capacitor 6) is equal to the charge down charge (discharging capacitor 6) during each cycle. Accordingly, if the duty cycle of a fixed frequency signal CKREF is fixed at 50/50, then the delay is fixed and is determined by the ratio of the up current IUP to the down current IDN as desired. DLL 1 is therefore usable to generate a delayed version of CKREF, where the amount of delay is programmable by setting the ratio of the IUP and IDN currents. Changes in duty cycle of CKREF, however, can cause changes in the delay time even if the frequency of CKREF remains constant and even if the ratio of IUP to IDN remains constant.
FIG. 3 (Prior Art) is a graph that shows how the delay time between CKREF and OUT3/3 changes as a function of the duty cycle of CKREF.